1. Field of the Invention
The present invention relates to a cyclic digital to analog converter, and more particularly, to a cyclic digital to analog converter in a pipeline structure having a shared charging capacitor.
2. Description of the Related Art
A cyclic digital to analog converter (CDAC) may be referred to as a cyclic switched capacitor digital to analog converter or a CDAC.
FIG. 1 is a diagram illustrating a conventional CDAC 100. Referring to FIG. 1, the CDAC 100 includes a CDAC core cell 110, an amplifier unit 130 and an output terminal 160. The CDAC 100 also includes switches S_1, S1_2, S2, S3, S4 and S5, three capacitors C1, C2 and C3, and an amplifier 150.
The CDAC core cell 110 may internally include an input unit 105. The input unit 105 receives a uniform level voltage VREF from one terminal and receives a ground voltage GND from another terminal. Here, the uniform level voltage VREF corresponds to a digital signal in a logic high level and the ground voltage GND corresponds to a digital signal in a logic low level.
When the digital signal in a logic high level is applied, a first input switch S1_1 is turned on (closed or connected), and the uniform level voltage VREF is transmitted to a first node N1. When the digital signal in a logic low level is applied, a second input switch S1_2 is turned on, and the ground voltage GND is transmitted to the first node N1.
When the uniform level voltage VREF or the ground voltage GND is applied to the first node N1, the first capacitor C1 charges according to the applied voltage. The second capacitor C2 is initially charged in a uniform initial value.
When the charging of the first capacitor C1 is complete, the second switch S2 is turned on. When the second switch S2 is turned on, charges in the first capacitor C1 and the second capacitor C2 are shared, and thus values of voltages in the first node N1 and a second node N2 are equalized. The second switch S2 is then turned off (opened or disconnected). Even when the second switch S2 is turned off, the equalized values of the voltages are maintained in the second node N2. As such, the charging and sharing operations are repeated until the least significant bit (LSB) to the most significant bit (MSB) of an input digital signal are all input.
In order to initialize the third capacitor C3, the fifth switch S5 is turned on for a very short time and then turned off. Continuously, the fourth switch S4 is turned on. The value of the voltage stored in the second node N2 is differentially output through the amplifier 150. The charges stored in the second capacitor C2 is transmitted to the third capacitor C3. Then, an analog voltage is output through an output terminal of the amplifier 150, and is driven to a load terminal of the output terminal 160.
Here, a uniform reference voltage VCOM is input to a − input terminal IN− of the amplifier 150. The uniform reference voltage VCOM has a value within an operation voltage range of the amplifier 150, and the value may vary according to the design specifications of the CDAC. The amplifier 150 differentially amplifies and outputs the uniform reference voltage VCOM and the voltage stored in the second node N2.
When the fourth switch S4 is turned on, a charge injection error is generated in the CDAC 100. The charge injection error is generated when the amount of currents flowing through both ends (i.e., terminals) of the fourth switch S4 are not in accord. When the fourth switch S4 is turned on, a charge flows into the fourth switch S4. The charge inflow differentiates the amount of currents flowing through the both terminals of the fourth switch S4, and accordingly, voltage levels of both terminals of the fourth switch S4 are different. The charge injection error or a non-linear charge injection error occurs when voltages of both terminals of a switch are different due to a charge inflow, even though the voltages should be the same when the switch is turned on.
Also, a mismatch between the second capacitor C2 and the third capacitor C3 affects an accuracy of the CDAC 100. The accuracy of the CDAC 100 is indicated by whether the CDAC 100 outputs a value of the analog voltage that accurately corresponds to a certain digital signal input. For example, when a four bit digital signal of 1101 is input, a value of the corresponding analog voltage should be 13/16. How close the value of the analog voltage is to 13/16 indicates the accuracy of the CDAC 100.
Hereinafter, an operation frequency of the CDAC 100 will be described. An operation cycle of the CDAC 100 includes a calculation period, which is a calculation performance period for changing a digital value to an analog value, and an amplifier settling period. In order to satisfy a target speed, the operation frequency of the CDAC 100 and a slew rate of the amplifier 150 should both increase. The increase of the operation frequency causes a larger bias current and power consumption. In a column driver of an LCD panel, for example, hundreds of CDACs 100 should be installed. Accordingly, a larger power consumption of each CDAC 100 leads to much larger overall power consumption of the entire LCD. The CDAC 100 illustrated in FIG. 1 is described in detail, for example, in U.S. Pat. No. 5,696,509, issued Dec. 9, 1997.
FIG. 2A is a diagram illustrating a conventional CDAC 200 in a pipeline structure. FIG. 2B is a diagram illustrating operations of the conventional CDAC 200 of FIG. 2A. Hereinafter, the conventional CDAC 200 in the pipeline structure will be described with reference to both FIGS. 2A and 2B.
In order to address the increase of the operation frequency and large power consumption of the CDAC 100 illustrated in FIG. 1, the pipeline structure of FIG. 2A may be used.
Referring to FIG. 2A, the CDAC 200 in the pipeline structure includes two CDACs. That is, each of a first CDAC block 220 and a second CDAC block 230 may be the CDAC 100 of FIG. 1.
When the first CDAC block 220 receives a digital signal and converts the digital signal to an analog value in the pipeline structure, the second CDAC 230 outputs a value which was pre-converted to an analog value. A first switch S1 201 and a fourth switch S4 204 are simultaneously turned on, and a second switch S2 202 and a third switch S3 203 are simultaneously turned on.
Referring to a time interval t2, during which the first switch S1 201 and the fourth switch S4 204 are turned on, the first CDAC block 220 (CDAC_1) receives a digital signal D3, and performs a calculation in order to convert the digital signal D3 to an analog value in operation 265. Simultaneously, the second CDAC 230 (CDAC_2) outputs a pre-calculated analog value to an output terminal Dout through the fourth switch S4 204 in operation 273.
Referring to a time interval t3, during which the second switch S2 202 and the third switch S3 203 are turned on, the first CDAC block 220 (CDAC_1) outputs the analog value of the digital signal D3 calculated in the time interval t2 through the third switch S3 203 in operation 267. Simultaneously, the second CDAC 230 (CDAC_2) receives a new digital signal D4 and performs a calculation in order to convert the digital signal D4 to an analog value in operation 275.
In the CDAC 200 in a pipeline structure, the two CDACs, i.e., the first CDAC block 220 and the second CDAC block 230, operate in a pipeline mode as illustrated in FIGS. 2A and 2B. Accordingly, calculation and output operations of the 200 CDAC can be performed throughout the entire cyclic period. Consequently, operation frequency of the CDAC 200 and pressure on the speed of an amplifier can be reduced. Also, large power consumption due to increase of the operation frequency can be reduced. Thus, the CDAC 200 in a pipeline structure addresses to some extent the problem of large power consumption in the CDAC 100 of FIG. 1.
However, the CDAC 200 in a pipeline structure separately uses two entirely independent CDAC blocks, CDAC block 220 and CDAC block 230. Accordingly, the size of the CDAC 200 is twice the size of the CDAC 100. In an LCD driver, the size of a CDAC is an important factor in determining the ultimate size of the LCD driver. Therefore, using a larger CDAC is against the current trend toward smaller LCDs. In addition, the charge injection error described above still occurs in the CDAC 200.